Our work "A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation" has been accepted by ASP-DAC 2027!
Sep 1, 2026
Our work "PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimization" has been accepted by TODAES!
Aug 13, 2026
Our work "TAP-MAC: Low-Power Optimization of Multipliers and Multiply-Accumulators via Topology-Aware Power Modeling" has been accepted by ICCAD 2026!
Jul 11, 2026
Our work "PCB-Bench: Benchmarking LLMs for Printed Circuit Board Placement and Routing" has been accepted by ICLR 2026!
Jan 26, 2026
Our work "Efficient Continuous Logic Optimization with Diffusion Model" has been accepted by DAC 2025!
Feb 15, 2025
Our work "RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction" has been accepted by TODAES!
Dec 13, 2024
Our work "A Holistic FPGA Architecture Exploration Framework for Deep Learning Acceleration" has been accepted by ASP-DAC 2025!
Sep 8, 2024
Our work "UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators" has been accepted by ICCAD 2024!
Jun 26, 2024