🎉 One paper accepted by ASP-DAC 2027!
Our work “A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation” has been accepted by ASP-DAC 2027!
About Me
I am a Ph.D. student at the Microelectronics Thrust of The Hong Kong University of Science and Technology (Guangzhou), advised by Prof. Yuzhe Ma. Previously, I earned my M.Phil. degree from The Hong Kong University of Science and Technology (Guangzhou) in 2024 and my B.Eng. degree from Shanghai University in 2022.
Interests
- AI for chip design
- Electronic design automation (EDA)
- Inverse design
- Physical design
- Large Language Model (LLM)
Education
Ph.D. Microelectronics
HKUST(GZ)
M.Phil. Microelectronics
HKUST(GZ)
B.Eng. Electrical Engineering and Automation
SHU
📑 Featured Publications
📚 Recent Publications
(2026).
A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation.
In ASP-DAC 2027.
(2026).
PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimization.
TODAES.
(2026).
TAP-MAC: Low-Power Optimization of Multipliers and Multiply-Accumulators via Topology-Aware Power Modeling.
In ICCAD 2026.
(2026).
PCB-Bench: Benchmarking LLMs for Printed Circuit Board Placement and Routing.
ICLR 2026.
(2025).
Efficient Continuous Logic Optimization with Diffusion Model.
In DAC 2025.
📰 Recent News
🎉 One paper accepted by TODAES!
Our work “PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimization” has been accepted by TODAES!
🎉 One paper accepted by ICCAD 2026!
Our work “TAP-MAC: Low-Power Optimization of Multipliers and Multiply-Accumulators via Topology-Aware Power Modeling” has been accepted by ICCAD 2026!
🎉 One paper accepted by ICLR 2026!
Our work “PCB-Bench: Benchmarking LLMs for Printed Circuit Board Placement and Routing” has been accepted by ICLR 2026!
🎉 One paper accepted by DAC 2025!
Our work “Efficient Continuous Logic Optimization with Diffusion Model” has been accepted by DAC 2025!
🎉 One paper accepted by TODAES!
Our work “RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction” has been accepted by TODAES!
🎉 One paper accepted by ASP-DAC 2025!
Our work “A Holistic FPGA Architecture Exploration Framework for Deep Learning Acceleration” has been accepted by ASP-DAC 2025!
🎉 I have successfully passed the M.Phil. thesis examination!
Congratulations to myself!
🎉 One paper accepted by ICCAD 2024!
Our work “UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators” has been accepted by ICCAD 2024!